The present invention relates to a circuit composed of semiconductor elements, and more particularly to a digital circuit employing insulated gate field effect transistors (IGFET's).
At present the most common dynamic random access memory (hereinafter abbreviated as RAM) is of the 2-clock multi-address input system. Currently, RAM's of 4K, 16K and 64K bits packaged in a standard 16-pin package are being produced, and in the future, developments of RAM's of 256K and 1M bits packaged in the 16-pin package employing this system are expected. This memory system is detailed in U.S. Pat. No. 3,969,706. The two clocks are normally called RAS (Row Address Strobe) and CAS (Column Address Strobe). The RAS contributes to activation of an X-address inverter buffer, an X-decoder (row) buffer and a memory cell sense amplifier, and the CAS contributes to activation of a Y-address (column) inverter buffer, a Y-decoder buffer and a data input/output bus amplifier and also achieves control of the output state.
In a RAM of this system, an operation called RAS ONLY REFRESH can be effected, in which refresh is achieved by activating only the RAS while maintaining the CAS at a high level, that is, in a reset condition. In addition, it is possible to achieve an operation called HIDDEN REFRESH, in which after output data have been derived in a normal read cycle, only the RAS is reset while maintaining the CAS intact at a low level, that is, in an activated condition, subsequently activations of the RAS are repeated, and thus refresh can be achieved while maintaining the output data intact.
However, problems occurring in common to these operation modes are to maintain a logic level in an output system for a long period of time. Since the maintenance of a logic level is basically achieved by making use of electric charge on an electrostatic capacitance, the level will be attenuated with time, and hence it has been difficult to maintain a logic level in an output system over a relatively long period.